The present invention relates to clock signal generation circuits and methods, and more particularly, to clock signal generation circuits and methods that provide duty cycle control.
Many systems, including semiconductor memory devices, such as RDRAM (Rambus Dynamic Random Access Memory) and DDR (Double Data Rate) memory devices, systems for processing video signals and/or audio signals, and communication systems, include a clock generation circuit that uses a DLL (Delay Locked Loop) to generate an accurate clock signal. A typical clock signal generation circuit processes an input clock signal and generates a new clock signal with a predetermined duty factor. The duty factor is a percentage of a value obtained by dividing a time of a logic high pulse width of a clock signal by a period of the clock signal. A clock signal with a duty factor of 50% is used in many systems, but a clock signal with a different duty factor may be needed for some circuits. In order to ensure normal system operation, a clock signal generation circuit for generating a clock signal with a constant duty factor may be used.
FIG. 1 is a block diagram of a conventional duty cycle correcting clock signal generation circuit 100. Referring to FIG. 1, the circuit 100 includes a DLL 110, an inverter 120, and a phase mixer 130. A clock signal CKIN input to the circuit 100 may have a certain jitter due to duty cycle distortion. The clock signal generation circuit 100 outputs a new clock signal CKOUT having a duty factor of approximately 50%. The DLL 110 produces a signal DO that is delayed (for example, 180°) with respect to the input clock signal CKIN using a feedback signal DOB produced by the inverter 120 in order to correct a phase of the output clock signal CKOUT. The signal DOB produced by the inverter 120 is mixed with the input clock signal CKIN in the phase mixer 130, which generates an output clock signal CKOUT. The circuit 100 is disclosed in detail in Korean Laid-open Patent No. 01-0095537 to Gyu-Hyun Kim and Jung-Bae Lee.
The conventional clock signal generation circuit 100 can reduce jitter due to internal noise of the DLL 110, but can increase a jitter of the input clock signal CKIN arising from internal noise of the DLL 110, thereby causing jitter peaking. FIG. 2 is a view explaining jitter peaking in the DLL 110. As shown in FIG. 2, jitter peaking is a phenomenon in which when a jitter of δ1 exists in an input clock signal CKIN, a phase-corrected value of δ2 is added to the jitter of δ1 by the DLL 110, thereby generating a greater jitter in an output clock signal CKOUT.
An example using an oscillator-type phase filter to remove such jitter peaking, is described in an article “Jitter Transfer Characteristics of Delay-Locked Loops-Theories and Design Techniques” by Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton and Ramesh Senthinathan, IEEE JSSC vol. 38, NO. 4, APRIL 2003. However, using the oscillator-type phase filter can change a frequency of the output clock signal CKOUT and cause jitter accumulation, which can produce a greater jitter.